That is super cool. I wrote to SGS-Thomson when I was in highschool and they sent me what felt like a refrigerator box of manuals for the 400 through the 9000.

That is super cool. I wrote to SGS-Thomson when I was in highschool and they sent me what felt like a refrigerator box of manuals for the 400 through the 9000. Huge transputer fan. The simplicity was striking, and that you could construct a system that could handle huge numbers of threads communicating across the network with almost no "system software" in the way was mind blowing. Most famously, Gene Amdahl started https://en.wikipedia.org/wiki/Trilogy_Systems https://en.wikipedia.org/wiki/Trilogy_Systems in the 80s to explore this idea. The calculus changes when you don't have to dice the wafer, packaging, etc. I'd say that we clock things now at the highest speed that we can safely remove heat, so these wafer scale chips, we trade frequency for area and need/should clock them much slower. At large production runs, the wafer in a Cerebras is 20k each for a system costing millions and the primary engineering feat is still cooling. I'd love to see a WSI system utilizing NTV (near threshold voltage) logic. https://semiengineering.com/near-threshold-computing-2/ https://semiengineering.com/near-threshold-computing-2/ Another interesting design pattern that has arisen is that Cerebras, Esperanto, Tenstorrent, and InspireSemi are all mesh networks using message passing. What kinds of things did you work on at Inmos?