The silicon required to implement SMT takes up space, and Intel clearly thinks that they have a better use for it: The P-core tile is on the smallest, most exp

The silicon required to implement SMT takes up space, and Intel clearly thinks that they have a better use for it: The P-core tile is on the smallest, most expensive node, right? So Intel is probably getting more P-core tiles per wafer by removing SMT, and making up for it by giving you more of “other stuff” that comes from cheaper wafers with higher yield. As long as they are honest and you are getting performance that matches your expectations, this is fine.