Using up a lot of encoding space for four registers is indeed a problem, but it's a different problem. Even if you restrict the instruction to Fd ← Fd + (Fs1 *

Using up a lot of encoding space for four registers is indeed a problem, but it's a different problem. Even if you restrict the instruction to Fd ← Fd + (Fs1 * Fs2) and/or Fd ← Fs1 + (Fd * Fs2) (the RISC-V Vector extension provides both) you still have to read three registers.