I think it's easier to see if you jump up 1 level of abstraction from transistors to logic gates. Imagine an adder made up of logic gates. The gates aren't inh

I think it's easier to see if you jump up 1 level of abstraction from transistors to logic gates. Imagine an adder made up of logic gates. The gates aren't inherently synchronous - they don't have a clock input - signals appear at their inputs and some time later propagate to their outputs. To make the adder synchronous you need flip flops at the inputs/outputs and a clock. If you squint a bit you can view most designs as blobs of async logic sandwiched between sync elements (gated by the clock). We can see that a signal might have to go through a lot of gates/transistors between flip-flops and so the gates (and their underlying transistors) will necessarily need to be able to switch faster than the clock.