My conclusion from this: There won't be a close-to-optimal ISA for high perf (big cores) in the near-to-mid future unless there is a completely new market creat

My conclusion from this: There won't be a close-to-optimal ISA for high perf (big cores) in the near-to-mid future unless there is a completely new market creates demand. + Nobody bothers documenting publicly semantics and time information ?except Agner Fog?, let alone design process. + Investment costs are too high. + No sane way to lower without efficient emulation compatibility inheriting the very same design flaws. + Formal models with explicit time information help, but few economic incentive and a lot incentives against beyond simulations + Smaller ones like RISC5 may be feasible, see sel4 project (embedded/security domains) I wonder if learning an optimal ISA from given ones would require optimizing 1. time semantics, 2. instruction semantics, 3. source code under uncertain distributions from given examples or if it is completely intractable.