26 ms·
My concept is SmallTalk-ish. Control flow, object frames, and GC in one unit and all higher level math, array, function, FPGA, GPU cell are in one or more adjo
by kmacleod 3y ago
My concept is SmallTalk-ish. Control flow, object frames, and GC in one unit and all higher level math, array, function, FPGA, GPU cell are in one or more adjoined units. The control unit keeps the higher level units fed in a hyper-threading sense. Both unit sets are independently scalable so a unit-pair can be as small as a 8x8 pixel block in a display in a mesh network, an 8-, 12-, or 16-bit device controller, a 32-bit display GPU driver for the pixel block units, etc. All cores talk to other control cores through message passing, with object ID mapping at the interface. Security for small cores is also handled generally at interfaces through capabilities (access to certain core object mappings). The highest levels run as processes on existing OSs.