4 ms·
I very well balanced article. My biggest quibble would have been mentioning the self-synchronizing[1] nature of the variable length instructions that make RISC
by Symmetry 3y ago
I very well balanced article. My biggest quibble would have been mentioning the self-synchronizing[1] nature of the variable length instructions that make RISC-V easier to decode in batches than x86.
[1]https://en.wikipedia.org/wiki/Self-synchronizing_code https://en.wikipedia.org/wiki/Self-synchronizing_code
- CodesInChaos 3y agoHow is RISC-V self synchronizing? The encoding described in Chapter 1.5 Base Instruction-Length Encoding isn't self-synchronizing in general.
- saagarjha 3y agoInterestingly, x86 is also kind of "naturally self-synchronizing" for real-world code, as you'll notice if you try to disassemble at an arbitrary address in GDB. It's not perfect of course–you can always craft a code sequence that is malicious–but in general it's a useful property, if not for instruction decode in a processor.