It already uses 32 registers, just like RISCV, but only half of those can be used to access memory. It mostly cuts down on the number of load/store and branch e

It already uses 32 registers, just like RISCV, but only half of those can be used to access memory. It mostly cuts down on the number of load/store and branch encodings. The address registers are "intelligent" and can auto-de/increment, while branches have been mostly eliminated from the ISA and don't use many encodings. But sure, there is always demand for new instructions, and there is limited space. I imagine things like SIMD could be shoved into the secondary instruction set. Though I imagined that secondary ISA would by default be a Forth jump list, it would come virtually for free.