3 ms·

Is anyone trying to write ISA for specific programing languages, like the lisp machines of old? Would RiskV be amenable to have language-specific customization

by aredox 3y ago

Is anyone trying to write ISA for specific programing languages, like the lisp machines of old? Would RiskV be amenable to have language-specific customizations or peripheral accelerators?

phi-go 3y ago
RISC-V is designed to provide op-code space for custom instructions, so it can be extended for specific tasks.
JonChesterfield 3y ago
I think I read something about Apple making reference counting faster using hardware. Machine learning asics are prone to having instructions that correspond to activation functions. tanh, sigmoid etc. A reasonable approach is to take a risc ISA and add domain specific instructions onto it. That gets you straightforward codegen and implementation for the 90% case and magic instructions to make the important path very fast.
kmacleod 3y ago
My concept is SmallTalk-ish. Control flow, object frames, and GC in one unit and all higher level math, array, function, FPGA, GPU cell are in one or more adjoined units. The control unit keeps the higher level units fed in a hyper-threading sense. Both unit sets are independently scalable so a unit-pair can be as small as a 8x8 pixel block in a display in a mesh network, an 8-, 12-, or 16-bit device controller, a 32-bit display GPU driver for the pixel block units, etc. All cores talk to other control cores through message passing, with object ID mapping at the interface. Security for small cores is also handled generally at interfaces through capabilities (access to certain core object mappings). The highest levels run as processes on existing OSs.
mbitsnbites 3y ago
I would say that all modern "general purpose" ISAs (and microarchitectures) are optimized for C (and C++). That's what most OS:es and high profile applications are written in (web browsers - and by extension electron apps, compilers, games, content creation, etc).

by aredox 3y ago

Is anyone trying to write ISA for specific programing languages, like the lisp machines of old? Would RiskV be amenable to have language-specific customizations or peripheral accelerators?

phi-go 3y ago

RISC-V is designed to provide op-code space for custom instructions, so it can be extended for specific tasks.

JonChesterfield 3y ago

I think I read something about Apple making reference counting faster using hardware. Machine learning asics are prone to having instructions that correspond to activation functions. tanh, sigmoid etc. A reasonable approach is to take a risc ISA and add domain specific instructions onto it. That gets you straightforward codegen and implementation for the 90% case and magic instructions to make the important path very fast.

kmacleod 3y ago

My concept is SmallTalk-ish. Control flow, object frames, and GC in one unit and all higher level math, array, function, FPGA, GPU cell are in one or more adjoined units. The control unit keeps the higher level units fed in a hyper-threading sense. Both unit sets are independently scalable so a unit-pair can be as small as a 8x8 pixel block in a display in a mesh network, an 8-, 12-, or 16-bit device controller, a 32-bit display GPU driver for the pixel block units, etc. All cores talk to other control cores through message passing, with object ID mapping at the interface. Security for small cores is also handled generally at interfaces through capabilities (access to certain core object mappings). The highest levels run as processes on existing OSs.

mbitsnbites 3y ago

I would say that all modern "general purpose" ISAs (and microarchitectures) are optimized for C (and C++). That's what most OS:es and high profile applications are written in (web browsers - and by extension electron apps, compilers, games, content creation, etc).