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It seems most people designing an ISA will do RISC, but when I designed the ISA for the Vircon32 CPU I instead took 32-bit x86 as a basis. I had done ASM in MS-
by carra 3y ago
It seems most people designing an ISA will do RISC, but when I designed the ISA for the Vircon32 CPU I instead took 32-bit x86 as a basis. I had done ASM in MS-DOS so it was what I knew best. I simplified it a lot in various ways but one of them was key: it cannot split registers to use 8 or 16 bit data. This alone was enough for me to reduce the opcode list to just 64 (6 bits, so no unused opcodes). And that is even adding a few math instructions to handle floats.
- mbitsnbites 3y agoVircon32 looks very nice! So what did you do w.r.t. addressing modes? Do you have memory-memory operations? Is it a load/store architecture? I found the CPU specification (https://github.com/vircon32/Vircon32Documents/blob/main/Specification/English/PDF%20documents/Spec%20part%203%20-%20The%20processor%20(CPU).pdf https://github.com/vircon32/Vircon32Documents/blob/main/Spec...), but I couldn't find an ISA specification.
- carra 3y agoThank you! The CPU document should cover everything about the ISA itself. There are 8 addressing modes, which are covered in pages 19 and 20. MOV is the only instruction that explicitely uses them. Other instructions, at most, can only choose to either use registers or an immediate value. There are no capabilities like DMA, so memory-memory operations are not really possible with the only exception of instruction MOVS which acts as a supposed MOV [DR], [SR].