4 ms·

All three ISAs referenced as inspiration have the same (lack of) addressing modes: base register plus offset, and that's it. You don't want to argue with Seymo

All three ISAs referenced as inspiration have the same (lack of) addressing modes: base register plus offset, and that's it. You don't want to argue with Seymour Cray. Or with John Mashey, for that matter.

renox 3y ago
I disagree: a lot of CPU ISA design decisions are a result of the state of the technology available to implement these CPU. As the technology change, design decisions should be revisited: see here https://queue.acm.org/detail.cfm?id=3639445 https://queue.acm.org/detail.cfm?id=3639445 for someone saying the same thing. POWER is an example of a modern "RISC" architecture with lots of addressing mode..
mbitsnbites 3y ago
Hi Bruce! :-) Well, to be fair I said "inspired by", not "copied from". BTW, I'm not trying to bash RISC-V (although it may come across that way sometimes).
snvzz 3y ago
>You don't want to argue with Seymour Cray. Or with John Mashey, for that matter. Sure, yet they definitely want to argue against the third one, as unlike the other two, it isn't an historically significant ISA that has now been replaced by something else. Particularly, if they're implying there's something wrong with it and that they can do better, they should own up to that. Document what's wrong. Prove their way actually is better. As it is right now, I have to understand it is just another instance of "the addressing modes I like having aren't there, so I made an ISA with them". A common occurrence, unfortunately.
- mbitsnbites 3y ago
  > the addressing modes I like having aren't there, so I made an ISA with them Not really... Se my other comment: https://news.ycombinator.com/item?id=39042048 https://news.ycombinator.com/item?id=39042048 I'm not alone. Many others with far more experience and know-how in both ISA design and micro architecture design have the same opinions. It's not that the RISC-V solution is "wrong" or "bad", it's just that it was designed to cater to all needs, including the super-simple very low end (the kind that you can implement from scratch in a weekend). I think that RISC-V does that very well, but it comes at a cost. Being good at everything pretty much precludes being the best in every segment. MRISC32 tries to be one step up from RISC-V in terms of performance targets (well, realistically MRISC64 would be that ISA), but one step down from AArch64 in terms of complexity.

renox 3y ago

I disagree: a lot of CPU ISA design decisions are a result of the state of the technology available to implement these CPU. As the technology change, design decisions should be revisited: see here https://queue.acm.org/detail.cfm?id=3639445 https://queue.acm.org/detail.cfm?id=3639445 for someone saying the same thing. POWER is an example of a modern "RISC" architecture with lots of addressing mode..

mbitsnbites 3y ago

Hi Bruce! :-) Well, to be fair I said "inspired by", not "copied from". BTW, I'm not trying to bash RISC-V (although it may come across that way sometimes).

snvzz 3y ago

>You don't want to argue with Seymour Cray. Or with John Mashey, for that matter. Sure, yet they definitely want to argue against the third one, as unlike the other two, it isn't an historically significant ISA that has now been replaced by something else. Particularly, if they're implying there's something wrong with it and that they can do better, they should own up to that. Document what's wrong. Prove their way actually is better. As it is right now, I have to understand it is just another instance of "the addressing modes I like having aren't there, so I made an ISA with them". A common occurrence, unfortunately.

mbitsnbites 3y ago
> the addressing modes I like having aren't there, so I made an ISA with them Not really... Se my other comment: https://news.ycombinator.com/item?id=39042048 https://news.ycombinator.com/item?id=39042048 I'm not alone. Many others with far more experience and know-how in both ISA design and micro architecture design have the same opinions. It's not that the RISC-V solution is "wrong" or "bad", it's just that it was designed to cater to all needs, including the super-simple very low end (the kind that you can implement from scratch in a weekend). I think that RISC-V does that very well, but it comes at a cost. Being good at everything pretty much precludes being the best in every segment. MRISC32 tries to be one step up from RISC-V in terms of performance targets (well, realistically MRISC64 would be that ISA), but one step down from AArch64 in terms of complexity.