OK, thanks. So the problem is that transistor density is going up faster than pin density? Makes sense. I guess one approach to that is a bigger die size, so y

OK, thanks. So the problem is that transistor density is going up faster than pin density? Makes sense. I guess one approach to that is a bigger die size, so you end up with a fixed transistor/cm^2? That would mean die sizes doubling with Moore's law I guess. So you'd want other ways of packing them in (use the flipside of the mobo, try 3d arrays and suffer heat problems). Or the cores come with attached (non-shared) RAM, which is of course where we are with adding cache. Other random thoughts: why have memory busses stayed parallel when peripheral busses (scsi, usb) have gone serial? That would reduce pin count for a connection? Can we avoid going to full 'macro' pins for the CPU-memory bus (and thus pack more pins into the same area for memory connections)? Instead have a smaller, denser collection of pins which are attached as a group to each memory connector? Sorry for being clueless and thinking aloud, but it's an interesting problem.