[citation needed] Do you have anything concrete to support "nowhere near where they are for x86 or M1"? I literally eyeball RISC-V code all day long for a livi

[citation needed] Do you have anything concrete to support "nowhere near where they are for x86 or M1"? I literally eyeball RISC-V code all day long for a living and it's not like there a massive performance lost to the compiler.