3 ms·
I believe that UC writes are indeed slow, but are not actually fully synchronous. PCI "write posting" is a thing: > Writes to MMIO space allow the CPU to conti
by oasisaimlessly 3y ago
I believe that UC writes are indeed slow, but are not actually fully synchronous. PCI "write posting" is a thing:
> Writes to MMIO space allow the CPU to continue before the transaction reaches the PCI device. HW weenies call this “Write Posting” because the write completion is “posted” to the CPU before the transaction has reached its destination.
https://www.kernel.org/doc/html/v5.6/PCI/pci.html https://www.kernel.org/doc/html/v5.6/PCI/pci.html
- loeg 3y agoYeah, PCI writes can be posted. It's still very very slow and will end up using an inefficient small transaction size on the PCIe side of things. And posting doesn't help with reads, of course. PCI devices that are cache coherent and can cache snoop and otherwise work with WB cache mode can be written a lot faster. UC writes are something like sequentially consistent (program order reordering with other operations is not allowed) which limits the OoO / superscalar magic the CPU can otherwise do to make code fast. I like this series as an intro: https://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1 https://xillybus.com/tutorials/pci-express-tlp-pcie-primer-t...