The NPUs are effectively hard IP blocks on xilinx FPGA fabric (i.e. there are close to no LUTs there - the chip takes in Xilinx bitstream but the only available

The NPUs are effectively hard IP blocks on xilinx FPGA fabric (i.e. there are close to no LUTs there - the chip takes in Xilinx bitstream but the only available resources are hard IP blocks) There's also Xtensa cores (audio coprocessor) and ARM cores included (PSP, Pluton, and I think there's extra ARM coprocessor for handling some sensor stuff optionally)