Assuming it's the same 'tile' tech they're using in their GPUs, it's a chiplet with a Xilinx FPGA with hard IP blocks where appropriate.[1] So it's probably a

Assuming it's the same 'tile' tech they're using in their GPUs, it's a chiplet with a Xilinx FPGA with hard IP blocks where appropriate.[1] So it's probably a matter of reverse engineering the bitstream as well as the functionality of those hard IP blocks. [1] My bet would be that it's mostly (90%+) hard IP blocks since most of the functionality for deep neural nets is well known and the FPGA logic just glues everything together and gives them some wiggle room as architectures evolve.