Hmm looking at the architecture it seems like it would be though to create performant tooling quickly (especially if it needs reverse engineering), the VLIW/RIS

Hmm looking at the architecture it seems like it would be though to create performant tooling quickly (especially if it needs reverse engineering), the VLIW/RISC ISA along with a CUDA-like threading model, and the tensor-flow (pun intended) for efficient cascading of neighboring AIE. On the other hand this arch does give it a very high ceiling so I get why they would go for it.