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The way we use transistors does not leave any room for tri-level circuits to be more efficient. The high clock speeds we get rely on fast switching of power le

The way we use transistors does not leave any room for tri-level circuits to be more efficient. The high clock speeds we get rely on fast switching of power levels, this is generally done by targeting a voltage well beyond the switching threshold. The smallest transistors we produce generally have a big variability in amplification, they would be really bad for analogue circuitry, but in digital they just have to amplify enough, and it is ok if some of them amplify way better than that. Now consider tri-state, we have to target a voltage in the middle band if we are to produce the middle signal, so less room for over-targeting means slower switching. We probably also need to supply the whole circuit a higher voltage to make proper room for the signal levels, that is a big L in efficiency. One could build a circuit with three levels of input current, but that ends up more or less doubling the transistor count, so not an obvious win. I guess that is what the Setun did. If adding this complexity to a tube doesn't increase its cost much I guess that makes sense, but in the transistor world it is just a doubling.

bgnn 3y ago
Well, the way we use CMOS logic is like this. But we have a bunch of other logic families inplemented with MOSFETs. Dynamic logic is seldom complementary. CML too. There's no reason to not have 3-state CML. Ternary logic is used in data converters (Analog-to-digital and digital-to-analog) with succes. This is because these circuits are often differential, so for each 1 there is a -1 on the complementary side. Let's say it's a current steering DAC. For 1 the positive end will sink +1 unit current while negative end is sourcing +1 (effectively -1). We get -1 if we flip the positive and negative. 0 can be created by turning off the currents. The beauty of it is the 3-levels we created are inherently linear, which doesn't extend to higher bases! The DAC unit in this example is in logic terms a CML ternary inverter! It doesn't consume any power when in 0 state, so it improves CML power cobsumption too (>50% for uniform data activity). Now we established that it is possible to implement ternary logic: why is it not used? Because CMOS logic only consumes power during transition (dynamic power) while CML consumes quite a bit higher static power always. Actually CML can work at much higher speeds but it's gobe out of fashion because Moore's law till recently gave more transistors in the same area operating faster than the previous generation. When the Moore's law is died a slow death we went for increasing the die sizes by doing more in parallel than faster logic, because for complicated reasons CMOS is quite efficient when operating much slower than the speed limits of technology. This being said, there might be areas CMOS logic can be replaced but people don't do it because they don't think about the possibility. At least this is my observation in the field.
- NohatCoder 3y ago
  So you suggest transferring a trit using 3 wires. Wires for data transfer already take up a tremendous amount of space in a lot of CMOS logic. The primary point of CML is that a differential signal is interference resistant. Therefore it can be used for higher data rates in out-of-chip buses. It does not provider faster ALUs than CMOS.
  - bgnn 3y ago
    CML is mainly used for the speed. In a dense logic circuit interference doesn't matter that much since local routing is short. For the high speed clock generation (not only routing) and logic of high frequency data converters it's used because you can get 3-4x more speed compared to CMOS logic. If the Operation frequency is so high it's worth to switching to CML. That being said, my expertise isn't in ALU design but in data converter design for chip-to-chip interconnect. So you might be right that it doesn't result in a faster ALU for whatever other reason. I'd love to know why though. CMOS logic can also be differentially routed, and often is routed against interference. That + a full shield around sensitive routing like clock lines are standard practice. Both have the advantage of cobtaining the return current too. I'm not suggesting we switch to 3 wires for ternary. That would be stupid. Ternary CML is 2 wires. 10, 00, 01 with 11 being the forbidden state or having the same functionality of 00. This isn't efficient from routing perspective compared to single-ended CMOS. For large routing distances any kind of encoding can be used. I often use 2 dimensional (row-column) encoding/decoding for multi-GHz data busses travelling over long distances (like 500um to couple of mm). It's very easy to calculate the power cost and routing area cost of not using any emcoding with respect to doing an n-dimensional encoding (incl. the power and area of encoder/decoder). I even used a 3D encoding which reduced total routing channel area and power in a routing dense setup like 50%. Using a simple kind of coding like parity bit and multiplying the data with a random sequence is also used against interference but people often don't do this and regret it.. Anyhow, the point I'm trying to make is local logic and long distance routing are two problems with different optimization parameters.

bgnn 3y ago

Well, the way we use CMOS logic is like this. But we have a bunch of other logic families inplemented with MOSFETs. Dynamic logic is seldom complementary. CML too. There's no reason to not have 3-state CML. Ternary logic is used in data converters (Analog-to-digital and digital-to-analog) with succes. This is because these circuits are often differential, so for each 1 there is a -1 on the complementary side. Let's say it's a current steering DAC. For 1 the positive end will sink +1 unit current while negative end is sourcing +1 (effectively -1). We get -1 if we flip the positive and negative. 0 can be created by turning off the currents. The beauty of it is the 3-levels we created are inherently linear, which doesn't extend to higher bases! The DAC unit in this example is in logic terms a CML ternary inverter! It doesn't consume any power when in 0 state, so it improves CML power cobsumption too (>50% for uniform data activity). Now we established that it is possible to implement ternary logic: why is it not used? Because CMOS logic only consumes power during transition (dynamic power) while CML consumes quite a bit higher static power always. Actually CML can work at much higher speeds but it's gobe out of fashion because Moore's law till recently gave more transistors in the same area operating faster than the previous generation. When the Moore's law is died a slow death we went for increasing the die sizes by doing more in parallel than faster logic, because for complicated reasons CMOS is quite efficient when operating much slower than the speed limits of technology. This being said, there might be areas CMOS logic can be replaced but people don't do it because they don't think about the possibility. At least this is my observation in the field.

NohatCoder 3y ago
So you suggest transferring a trit using 3 wires. Wires for data transfer already take up a tremendous amount of space in a lot of CMOS logic. The primary point of CML is that a differential signal is interference resistant. Therefore it can be used for higher data rates in out-of-chip buses. It does not provider faster ALUs than CMOS.
- bgnn 3y ago
  CML is mainly used for the speed. In a dense logic circuit interference doesn't matter that much since local routing is short. For the high speed clock generation (not only routing) and logic of high frequency data converters it's used because you can get 3-4x more speed compared to CMOS logic. If the Operation frequency is so high it's worth to switching to CML. That being said, my expertise isn't in ALU design but in data converter design for chip-to-chip interconnect. So you might be right that it doesn't result in a faster ALU for whatever other reason. I'd love to know why though. CMOS logic can also be differentially routed, and often is routed against interference. That + a full shield around sensitive routing like clock lines are standard practice. Both have the advantage of cobtaining the return current too. I'm not suggesting we switch to 3 wires for ternary. That would be stupid. Ternary CML is 2 wires. 10, 00, 01 with 11 being the forbidden state or having the same functionality of 00. This isn't efficient from routing perspective compared to single-ended CMOS. For large routing distances any kind of encoding can be used. I often use 2 dimensional (row-column) encoding/decoding for multi-GHz data busses travelling over long distances (like 500um to couple of mm). It's very easy to calculate the power cost and routing area cost of not using any emcoding with respect to doing an n-dimensional encoding (incl. the power and area of encoder/decoder). I even used a 3D encoding which reduced total routing channel area and power in a routing dense setup like 50%. Using a simple kind of coding like parity bit and multiplying the data with a random sequence is also used against interference but people often don't do this and regret it.. Anyhow, the point I'm trying to make is local logic and long distance routing are two problems with different optimization parameters.