3 ms·
If a problem is parallelisable to that extent, are the cores actually hitting the same memory? (Presumably not, since you don't want multiple threads mutating t
by jbert 18y ago
If a problem is parallelisable to that extent, are the cores actually hitting the same memory? (Presumably not, since you don't want multiple threads mutating the same memory).
So the problem is really that we have:
[lots of cores] <=chokepoint of memory bus=> [lots of ram]
when we could have:
k times:
[1/k of our cores] <=single mem bus=> [1/k of our RAM]
That increases our aggregate memory bwidth by a factor of k. This has to be <= number of cores, and the problem being solved needs to be able to be partitioned into k chunks.
This is basically the clustering approach (individual proc+ram working on the problem), with the added advantage that we can leave some of the RAM unsplit so we get 'local' shared RAM for free.
- wmf 18y agoNo, the crossbar between the cores and memory controllers is not a problem. The problem is getting enough pins to attach more than four memory channels.
- jbert 18y agoOK, thanks. So the problem is that transistor density is going up faster than pin density? Makes sense. I guess one approach to that is a bigger die size, so you end up with a fixed transistor/cm^2? That would mean die sizes doubling with Moore's law I guess. So you'd want other ways of packing them in (use the flipside of the mobo, try 3d arrays and suffer heat problems). Or the cores come with attached (non-shared) RAM, which is of course where we are with adding cache. Other random thoughts: why have memory busses stayed parallel when peripheral busses (scsi, usb) have gone serial? That would reduce pin count for a connection? Can we avoid going to full 'macro' pins for the CPU-memory bus (and thus pack more pins into the same area for memory connections)? Instead have a smaller, denser collection of pins which are attached as a group to each memory connector? Sorry for being clueless and thinking aloud, but it's an interesting problem.
- wmf 18y agoI don't think the die size is a problem; AFAIK you can get very many pins out of a die, but getting them out of the package is where it gets expensive. FB-DIMM is already a serial-style high-frequency interconnect, but it isn't needed on low-end systems. I think this is really about business, not technology. What they want is not what the mainstream wants, so they must choose between cheap but memory starved systems or very expensive balanced systems. HPC people have been whining about killer micros for 20 years; this is just another version of it.