Thanks for the paper. > it'd be hard to build a competitive super-scalar chip (really for any ISA) without some verious[sic] serious investment "Hundreds of m

Thanks for the paper. > it'd be hard to build a competitive super-scalar chip (really for any ISA) without some verious[sic] serious investment "Hundreds of millions of dollars" cf. Mark Horowitz's Micro 35 keynote (https://www.youtube.com/watch?v=q8WK63joI_Y&t=1140s https://www.youtube.com/watch?v=q8WK63joI_Y&t=1140s) but if you look at the stack in his graph, it's obvious that the architecture portion of this is tiny. Making a superscalar core simulation (= "model"), or even an FPGA softcore, is within the reach of any sufficiently motivated individual and indeed there are several already. Of course the performance will be dramatically lower than a state of the art silicon implementation.