3 ms·
The disadvantage of single CCD is only half of available write memory bandwidth (using at least 1 computing thread on each CCD) [1]. [1] 16 B/cycle write vs 32
by kvemkon 3y ago
The disadvantage of single CCD is only half of available write memory bandwidth (using at least 1 computing thread on each CCD) [1].
[1] 16 B/cycle write vs 32 B/cycle read per CCD
https://www.servethehome.com/amd-ryzen-7000-series-platform-overview/amd-ryzen-7000-soc-architecture-soc-topology-with-2x-ccd-1x-iod/ https://www.servethehome.com/amd-ryzen-7000-series-platform-...
- _cenw 3y agoI'd wager the number of workloads that'd actually take advantage of operating on entirely different data on a per-thread basis is much, much lower than ones that benefit from massive L3 cache. And note that the infinity fabric and memory controller don't run on the same clock. The fabric tops out at ~2200 (though testing shows sweet spot at 2033 usually) and the memory controller usually tops out at ~3100 (DDR5-6200).
- kvemkon 3y agoThose might be not necessary 2 threads of one program, but 2 independent programs.