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Epyc has multiple L3 caches while Xeon has a unified L3. If the same TCP socket is accessed on multiple CCXes it would cause cache lines to bounce on Epyc which
by wmf 3y ago
Epyc has multiple L3 caches while Xeon has a unified L3. If the same TCP socket is accessed on multiple CCXes it would cause cache lines to bounce on Epyc which is pretty costly.
- briffle 3y agoI believe the new Xeon SP processors coming out are also based on the 'chiplet' design like the Epyc ones.
- wmf 3y agoThey are but Intel implements chiplets differently so they still have a single unified L3 cache.
- charleshn 3y agoOn that subject, it's worth knowing that with the default BIOS settings the whole socket shows up as a single NUMA node, which means that most workloads don't benefit from automatic NUMA balancing or manual NUMA-aware placement within a socket. One needs to set NPS "Nodes per socket" to e.g. 4 to have one NUMA node per quadrant, and potentially also "L3 cache as NUMA" to have one per CCX [0]. [0] https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/tuning-guides/58002_amd-epyc-9004-tg-hpc.pdf https://www.amd.com/content/dam/amd/en/documents/epyc-techni...