7 ms·

Makes me wonder what the m88k instruction set was like, sadly a quick search makes it look like the only programming manuals were (now expensive) physical books

• kragen 3y ago
  in terms of systems design it looks pretty decent: 32 gprs, 51 instructions, load-store architecture, 20 megahertz, one instruction per clock for alu instructions, hardware floating point coprocessor, can do fp and memory concurrent with alu instructions, hardware multiplier, delay slot bit in branches, separate instruction and data memory buses. the big thing not specified in the manual is the price; a 20-mips processor costing US$10000 in 01988 is different from a 20-mips processor costing US$10. but of course what killed it was powerpc apparently the mmu was a separate chip? with the cache on it? and that's why this manual doesn't document the page table structure? so it was only questionably a microprocessor
  • cmrdporcupine 3y ago
    of course what killed it was powerpc I thought it was already considered a failure before the arrival of the Power alliance? I seem to recall hearing about reliability etc problems with the few who tried it? I think NeXT went as far as building a box around it?
    • kragen 3y ago
      the 68000 had similar problems, you couldn't reliably restart an instruction after a page fault. the sun-1 worked around this by using two 68000s. as i understand it, usually you can work around reliability problems in cmos by stricter testing (at the fab, reducing yield), lower clocks, higher voltage, better bypassing and esd protection, longer setup and hold times, bigger heatsinks, derating industrial parts to commercial grade (or military parts to industrial grade), laser trimming, or occasionally higher clocks and/or lower voltage. not always, of course parts that don't work at all are often unrecoverable, except through ridiculous workarounds like the sun-1 (one computer for the price of two!) or the 286 return to real mode via a cpu full reset (https://retrocomputing.stackexchange.com/questions/11954/how-to-switch-an-80286-from-protected-to-real-mode https://retrocomputing.stackexchange.com/questions/11954/how...) but parts that work sometimes can often be babied enough to get them to work reliably
      • cmrdporcupine 3y ago
        yeah the 68k story is funny, I've heard that before, though I remembered it as Apollo that did that dual 68k trick. It always confused me why Motorola didn't just axe the original 68000 entirely when it released the 68010 (with the fix for the page fault mis-design). there was no reason to keep producing the former after the latter came out, and it couldn't have cost them any more to make the '010 and it was pin for pin compatible (I've stuffed an 010 in Atari STs here with 0 problems, for example).
        • kragen 3y ago
          i think i was misremembering which company it was and you're right pin-for-pin compatible parts always have some differences: power consumption, setup and hold times, ground bounce, slew rates, noise margins, hysteresis on slow transitions, drive strength, stability in the face of capacitive output loads, endurance when subjected to overvoltage or overcurrent conditions, etc. dave jones of eevblog did a video a few years ago https://youtu.be/1VlKoR0ldIE https://youtu.be/1VlKoR0ldIE about how he shipped a bunch of defective μCurrent burden-voltage-eliminating current sensors. in his tests it worked fine, but many of his customers started reporting inaccurate readings. after sufficient debugging, he figured out that the problem happened only when its output was connected to a voltmeter with a high input capacitance, which caused its output to oscillate, introducing both noise and an offset into the readings. it turned out that one of the op-amps was going into oscillation because it couldn't handle driving that much output capacitance, a common problems with op-amps, but why was this never a problem before? he'd switched over to a second source that made a chip meeting the same specifications, but which turned out to be more vulnerable to output oscillations so, when you put a pin-compatible chip into a design in place of the original part, you have to carefully test the result to ensure that it still works properly. most times it will, but if it doesn't, you could have a product recall on your hands. worse, your customers may be incorporating your product into their own products if you pull chips without warning, for example when you start producing competitive chips, every company who designed them into a product has to suddenly switch over to their supposedly pin-compatible replacements. some of them will have their products fail unless they redesign them. they will have to pull their products from the market. everyone who designed a product incorporating your original chip gets fired, and when they finally manage to get a new job, they swear to never again use a part from your company and that's why lots of companies have been producing the μa741 and its clones like the lm741 since 01968, and why out of the 15522 different op-amps that digi-key lists as in stock, 1397 are listed as 'obsolete' and another 1042 are listed as 'last time buy'. and it's why a z80 you buy from zilog today still uses hundreds of milliamps i'm not an electrical engineer, i just play one on hn
  • kragen 3y ago
    summary of instruction set from skimming: encoding: - fixed-width 32-bit instruction set; - the instruction encoding is a little odd, with 5 formats* (or more?) and the opcode split into two parts with a couple of register numbers between them, but nothing like the bizarreness of risc-v; - 16-bit immediates orthogonally available for all integer arithmetic and bitwise instructions (not just, say, addi); * 3-reg (incl. base+scaled-index, jmp, lots of other things), 10-bit-imm, 16-bit-imm (which arguably includes bb0/bb1/bcnd), crs/crd, base+imm integer: - 31 32-bit gprs plus a zero register; - r31 is conventionally the stack pointer, but there are no push, pop, load-multiple, store-multiple, preincrement, predecrement, postincrement, or postdecrement facilities, so there are no special hardware privileges for a stack pointer register to potentially have; - strangely, there are separate signed and unsigned add and subtract, which suggests that it's not two's-complement. that would be tooo bizarre for 01988 but i can't find any clarification anywhere. maybe it just affects how carries are handled? - there is an integer divide instruction, two actually; - though it doesn't have an arm-like optional barrel shift on operand 2, it does have a pdp-8-like optional bit inversion on it; - they remembered to include the extract- and set-bit-field instructions the arm forgot which were added in thumb(2?), and they even have fancy things like ffs and ffc, and due to the bit inversion option it even supports abjunction (and-not), or-not, and xnor; - in fact, the extract- and set-bit-field instruction can even read the offset and width from a register (they don't have to be immediate); - and shift-right and shift-left are special cases of them; - the manual suggests tricks with the add instruction and the zero register to manipulate the carry bit, but i don't see suggestions for how to emulate mov, which is odd; memory: - load-store architecture; - apparently no halfword or even byte load or store instructions, but the ld and st instructions have a type field which allows them to do signed and unsigned halfword and byte loads and stores, orthogonally, and even doubleword loads and stores; - if you set the b.o. bit in the psr (cr1), your loads and stores are little-endian, which i guess motorola thought smelled bad; - only two addressing modes (base+unsigned-immediate and base+scale×index-register, but they count the second one twice) which is a lot less than arm but still more than risc-v; they claim seven but that's because they're double-counting base+scaled-index and also counting their jump target types; - there's a lea instruction (lea) but it's not super-powerful because it only does those two modes, and the scale only goes up to 8; - unaligned access is not implemented, not even 4-byte-aligned access for doublewords, but there's an option to truncate the address instead of trapping (maybe useful for pointer tagging); - there's an external line to tell the mmu whether it's in supervisor or user mode, plus a bit in load/store instructions to tell supervisor-mode code to access user memory, so plausibly they could use separate memory mappings, though i don't know if the actual mmu they shipped does this; - there's apparently no instruction cache flush instruction, so i suspect the (off-chip) caches had to implement a very expensive i386-like memory model; control flow: - there's a delay slot on branches, but a bit to turn it off; - there is no condition code register, but there are compare instructions, which store their results in a gpr. it also has some compare-and-branch instructions like risc-v, some which trap to supervisor mode and some which branch pc-relative by a signed 18-bit offset (bb0, bb1, bcnd), but no branch-if-greater-than style instructions with two source registers; - nevertheless, the psr has a carry bit in it, which you can use with .ci or .co suffixes on arithmetic, just no carry-conditional branch instructions; - the call instruction (bsr/jsr) uses a link register (r1) instead of a stack; etc.: - built-in one-issue-per-cycle ieee-754 fpu, including gradual underflow, both signaling and non-signaling nans, and both 64- and 32-bit floats, but without transcendentals or even square root; - no obvious way for a kernel to avoid saving fpu state when context-switching from a task that didn't use it; - i don't think you can read or write the psr in user mode, so it's standardly virtualizable, but that also means you can't switch byte orders or misaligned access handling style in user mode; - however, you can set the fpcr in user mode, so you can change the rounding mode for your interval arithmetic library; - their only atomic instruction for smp synchronization is xmem, exchange register with memory, which is a bit weak (though not as bad as the 68000, which iirc only had test-and-set); - the suggested calling convention has 13 call-clobbered registers (8 for parameters); ...