2 ms·
I only know about xilinx specific, but even given the support for runtime updates to the FPGA logic that already exist in the xilinx kernels, there are serious
by johnea 3y ago
I only know about xilinx specific, but even given the support for runtime updates to the FPGA logic that already exist in the xilinx kernels, there are serious roadblocks to updating only portions of the FPGA array.
The logic must be very carefully implemented to allow over-writing only specific regions of the FPGA.
If you're re-flashing the entire logic array, it's pretty straightforward. If you want to leave some logic in and add an additional funcitonality, this is much more difficult.
This is really a limitaiton of the FPGA logic array implementation, not a linux shortcoming...
- jeffreygoesto 3y agoPartial reconfiguration is possible since twenty-something years but only a small percentage of problems really benefit from it, see i.e. https://www.fpgakey.com/tutorial/section742 https://www.fpgakey.com/tutorial/section742
- pantantrant 3y agoWhat percentage of problems would benefit from parallel reconfiguration? I'm raising money for an FPGA in my profile where programs aren't bottlenecked in FPGA reconfiguration but instead are reconfigured in parallel.
- jeffreygoesto 3y agoWithout really deep experience (my FPGA time ended 15ish years ago), I would say that granularity and frequency of the swapped out parts need to hit a sweet spot and you need to be able to hide that latency. If I understand you correctly, you tsrget the latter? But as with all pipelining you need do have an early trigger or lookahead.
- vitarnixofntrnt 3y ago[dead]