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> The largest chapter of the 1992 edition of this book dealt with the compiler translating Oberon programs into code for the NS32032 processor. This processor i
by zvmaz 3y ago
> The largest chapter of the 1992 edition of this book dealt with the
compiler translating Oberon programs into code for the NS32032 processor. This processor is now neither available nor is its architecture recommendable. Instead of writing a new compiler for some other commercially available architecture, I decided to design my own in order to extend the desire for simplicity and regularity to the hardware. The ultimate benefit of this decision is not only that the software, but also the hardware of the Oberon System is described completely and rigorously. The processor is called RISC. The hardware modules are decribed exclusively in the language Verilog.
I wonder how it compares to Nand To Tetris. Other than that, it seems really interesting. Has anyone read it?
- 082349872349872 3y agoIt's much less pedagogical than Nand to Tetris; if you need the background, read that first, then read this. (he eventually ported the hardware description to his own HDL, Lola)
- kragen 3y agooh i had no idea, i have to see this. does lola support any existing fpgas?
- 082349872349872 3y agosee https://people.inf.ethz.ch/wirth/Lola/index.html https://people.inf.ethz.ch/wirth/Lola/index.html IIUC, in its 1990s incarnation Wirth had been able to get bitstream formats, but this century everything was closed off, so now it transpiles to Verilog.
- i_don_t_know 3y agoProject Oberon describes the final system as it is. It’s not a tutorial that takes you step by step from the basics to a complete system.
- hnthrowaway0328 3y agoNand2Tetris is the perfect introduction project of this field that spans Hardware, OS and compiler design. That said, I completed the project and found it lacking depths and in-depth investigation of all topics. But this is what makes it the perfect introduction project. The University of Tokyo has a similar project that I believe can serve as a stepping stone. Check out the CPU experiment: https://ytsmiling.tech/2017/04/02/cpuex.html https://ytsmiling.tech/2017/04/02/cpuex.html If you don't like it (probably due to lack of documentation), at this stage you can also design your own projects. Basically a CPU sub-project that uses Verilog or any HDL, which leads to an OS and compiler project.
- retrac 3y agoAs another user said, it's not oriented towards a beginner. You would want some, maybe most, of the background in NAND 2 Tetris first. Chapter 16 about that mentioned processor for example, and it just throws you in the deep end with the Verilog code. Here's the CPU interface with the system bus, the registers, and how the multiplier unit works. The good part is the commentary about the design decisions and trade-offs. That is invaluable, because it is the wisdom of Niklaus Wirth, towards the end of his career, drawing on a lifetime of experience. He was one of those rare polymaths, with a broad and deep understanding, of both the circuitry, and the more abstract parts of CS. He always generalized, tried to understand the principle, and places things in their historical context and explains how they developed. Because it's Wirth, the history lesson is often based on personal experience. It produces a good synthesis, in my opinion. For example: > The second [interface] (MouseX) is included here for historical reasons. It was used by the computer Lilith in 1979, and used the same Mouse as its ancestor Alto (at PARC, 1975). It is distinguished by a very simple hardware without its own microprocessor, which is currently contained in most mice. This goes at a cost of a 9-wire cable. But today, microprocessors are cheaper than cables. We include this interface here, because it allows for a simple explanation of the principle of pointing devices.
- kragen 3y agothe wirth-the-risc processor is immensely simpler to describe and program than the tecs/nand2tetris processor, which borders on unusable. i've gone through the process of 'designing' the nand2tetris processor on nandgame, and i'm pretty sure the nand2tetris processor is simpler to wire up from gates. but the wirth-the-risc processor is a lot easier to get running on an fpga or, i bet, to simulate with verilator, because it uses a real hdl instead of something that someone who's never designed hardware thinks an hdl might look like. probably the nand2tetris processor would require less code in verilog if you coded it up, quite similar to chuck thacker's 'a tiny computer for teaching' https://www.cl.cam.ac.uk/teaching/1112/ECAD+Arch/files/Thacker-A_Tiny_Computer-3.pdf https://www.cl.cam.ac.uk/teaching/1112/ECAD+Arch/files/Thack... which is, like the nand2tetris processor, based on the dirty genitals nova architecture nand2tetris will get you from nand gates to tetris and to bytecode interpreters. but oberon will get you from synthesizable verilog (which can be easily converted into nand gates but almost never is) to a fully usable gui operating system that can recompile its own source code. sadly it cannot resynthesize its own fpga bitstream because you cannot run vivado on it (though i see 71bae0447c737f454371dcf3b84fc62c says below it can at least simulate its own hardware) a thing they both have in common is the lack of a usable name for the processor architecture
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