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Project Oberon: Design of an operating system, a compiler, and a computer [pdf]
- zengid 3y agoRIP Prof Wirth Side note: can we get a better tag on this to show it's a PDF file? I think the source is reputable but I always freak out when a url goes to a pdf.
- forgotpwd16 3y agoUsually links leading to pdf are denoted with [pdf] at the end.
- zengid 3y agoit wasn't formatted like this at the time
- userbinator 3y agoThe URL already ends in .pdf .
- gjvc 3y agoWhat, specifically, worries you about pdf files?
- cmplxconjugate 3y agoHis plea for lean software [1] is always worth a read. [1] https://cr.yp.to/bib/1995/wirth.pdf https://cr.yp.to/bib/1995/wirth.pdf
- i_don_t_know 3y agoThat's only the first half of the book. You can find all parts and software at: https://people.inf.ethz.ch/wirth/ProjectOberon/ https://people.inf.ethz.ch/wirth/ProjectOberon/
- jll29 3y agop. 59-75 covers the fast implementation of piece lists (recently covered on HN). (Just saying because there were many threads on how to represent text buffers for fast editing on HN: https://news.ycombinator.com/item?id=15381886 https://news.ycombinator.com/item?id=15381886 https://news.ycombinator.com/item?id=11244103 https://news.ycombinator.com/item?id=11244103 https://news.ycombinator.com/item?id=14129543 https://news.ycombinator.com/item?id=14129543 https://news.ycombinator.com/item?id=15387672 https://news.ycombinator.com/item?id=15387672 https://news.ycombinator.com/item?id=14046446 https://news.ycombinator.com/item?id=14046446 )
- zvmaz 3y ago> The largest chapter of the 1992 edition of this book dealt with the compiler translating Oberon programs into code for the NS32032 processor. This processor is now neither available nor is its architecture recommendable. Instead of writing a new compiler for some other commercially available architecture, I decided to design my own in order to extend the desire for simplicity and regularity to the hardware. The ultimate benefit of this decision is not only that the software, but also the hardware of the Oberon System is described completely and rigorously. The processor is called RISC. The hardware modules are decribed exclusively in the language Verilog. I wonder how it compares to Nand To Tetris. Other than that, it seems really interesting. Has anyone read it?
- 082349872349872 3y agoIt's much less pedagogical than Nand to Tetris; if you need the background, read that first, then read this. (he eventually ported the hardware description to his own HDL, Lola)
- kragen 3y agooh i had no idea, i have to see this. does lola support any existing fpgas?
- 082349872349872 3y agosee https://people.inf.ethz.ch/wirth/Lola/index.html https://people.inf.ethz.ch/wirth/Lola/index.html IIUC, in its 1990s incarnation Wirth had been able to get bitstream formats, but this century everything was closed off, so now it transpiles to Verilog.
- i_don_t_know 3y agoProject Oberon describes the final system as it is. It’s not a tutorial that takes you step by step from the basics to a complete system.
- hnthrowaway0328 3y agoNand2Tetris is the perfect introduction project of this field that spans Hardware, OS and compiler design. That said, I completed the project and found it lacking depths and in-depth investigation of all topics. But this is what makes it the perfect introduction project. The University of Tokyo has a similar project that I believe can serve as a stepping stone. Check out the CPU experiment: https://ytsmiling.tech/2017/04/02/cpuex.html https://ytsmiling.tech/2017/04/02/cpuex.html If you don't like it (probably due to lack of documentation), at this stage you can also design your own projects. Basically a CPU sub-project that uses Verilog or any HDL, which leads to an OS and compiler project.
- pjmlp 3y agoAfter this follow up on the Oberon System 3, with its Gadgets component model, and a mix of JIT/AOT compilers, "The Oberon companion - a guide to using and programming Oberon System 3" https://www.semanticscholar.org/paper/The-Oberon-companion-a-guide-to-using-and-Oberon-3-Fischer-Marais/00296fcdca9e9b317fe9cdc9a198662e76ccd52e https://www.semanticscholar.org/paper/The-Oberon-companion-a... You can access the source code from Rochus fork, https://github.com/rochus-keller/OberonSystem3 https://github.com/rochus-keller/OberonSystem3 Or the Active Oberon evolution, although not directly done by Niklaus Wirth, https://gitlab.inf.ethz.ch/felixf/oberon https://gitlab.inf.ethz.ch/felixf/oberon Screenshots and OS Manual, https://gitlab.inf.ethz.ch/felixf/oberon/-/blob/main/ocp/Documentation/A2Documentation.pdf?ref_type=heads https://gitlab.inf.ethz.ch/felixf/oberon/-/blob/main/ocp/Doc... Or Component Pascal and Blackbox IDE, created by a startup out of ETHZ https://blackboxframework.org/index.php https://blackboxframework.org/index.php
- Rochus 3y agoThe Active Oberon evolution started with the Active Object System (AOS) and the Bluebottle window manager; the source code of the last "Current" release can be accessed e.g. here: https://github.com/OberonSystem3/AOS_Bluebottle_Sources https://github.com/OberonSystem3/AOS_Bluebottle_Sources. If you want to study the source code, you can use this tool: https://github.com/Rochus-Keller/ActiveOberon https://github.com/Rochus-Keller/ActiveOberon.
- guidoism 3y agoI re-typeset the text in TeX and have a nicer looking PDF for those that care: https://github.com/guidoism/tex-oberon https://github.com/guidoism/tex-oberon
- zvmaz 3y agoI really liked reading the README. It shows that you are passionate about Project Oberon and the book. This in turn motivates me to read it. Thank you for your work.
- sydbarrett74 3y agoThank you for your hard work and dedication in keeping this alive.
- loup-vaillant 3y agoAwesome! I'm guessing there's a not-too-hard way to change change the paper format? I'm thinking of going to A5 so I can bind myself a nice book.
- kragen 3y agothank you so much this must have been a huge amount of work
- berkeleynerd 3y agoIs it possible to use this version of the book to follow along and build everything without having to source the original FPGA board Wirth was using?
- cxr 3y agoYes, but if you want to actually run the programs, you'll need an emulator.
- I_am_tiberius 3y agoIn an interview with Niklaus he was talking about a 500 page document...
- whartung 3y agoThe original 1992 book is longer. As mentioned earlier the code generation chapter is smaller because the RISC CPU is much simpler than the original. But, also, the original, I think, has much more source code. I don’t know if the original book contains the entirety of the system, but the new one seems to contain more highlights of interfaces and selected examples. It likely relies on the ubiquity of source availability on internet, which clearly was not the case in 1992.
- ikhare 3y agoBack when I took compilers in college we wrote a compiler for Oberon. I couldn’t quite find my original class site, but this one seems roughly right (from a few years before I took the class): https://cseweb.ucsd.edu/~wgg/CSE131B/ https://cseweb.ucsd.edu/~wgg/CSE131B/ It was a great teaching language.
- fmeyer 3y agoThe idea of an education computer is bugging my mind in the last 5 years. If you consider modern hardware and OS is practically impossible to have a simple enough machine that you could teach the young generation. Fantasy consoles like pico-8 are good options for programming, but not for understanding the hardware underneath. That way you still have school who use old architectures for teaching.
- bpye 3y agoA minimal RISC-V implementation is quite simple. There is a RISC-V implementation of xv6 - though that’ll require slightly more than the absolute minimum RISC-V implementation, specifically you’ll need CSRs, M, S and U mode and paging. If you don’t care about paged memory you could do with just M and U mode. I have a small rtos that targets some of the WCH microcontrollers with that configuration. It does use the PMP but even that isn’t really necessary.
- ysofunny 3y agowhy would anybody NOT care about paged memory? or maybe a better question is, why care about it? as far as I've understood, paged memory is a legacy from a time where cheap and fast memory wasn't a thing how feasible is it to get rid of memory pages? I guess the hardest thing would be untangling interprocess memory safety from pages??
- Veserv 3y agoThe answer is memory fragmentation. Process memory safety can theoretically be done with a different scheme such as hardware memory capabilities. You could probably even do demand paging if the memory capability is not a true pointer, but some sort of memory system coherent handle. But, as soon as a process wants to allocate a 1 GB chunk and you have 2 GB, but only in 64 KB chunks you have a problem. You could go around copying data to compact the physical memory, but now you have serious interference problems. You then run into the next problem of using say 32 MB in a "hot loop" in the middle of a 64 GB demand-loaded data structure on a 32 GB machine. You can not greedily load in the entire data structure from disk, so you need some sort of subset feature on your memory handles. But then what do you do about using two disjoint sections separated by over 32 GB? You need some way of having multiple subsets that correspond to physical addresses that do not respect the handle offset. Subset 1 corresponds to physical address range A and subset B corresponds to a uncorrelated physical address range B. Congratulations, you have reinvented memory mapping with extra steps.
- flamedoge 3y agopretty good to save for post apocalyptic renaissance
- abdellah123 3y agoThis is a jewel. Is there an attempt to repurpose oberon as a mobile "computer"?
- berkeleynerd 3y agoHas anyone updated the book to allow one work with newer FPGA boards?
- lincpa 3y ago[dead]