The goal is that none of the intermediate data spills - the only user of RAM is reading the input data. But for that, you're right, the workload must be split

The goal is that none of the intermediate data spills - the only user of RAM is reading the input data. But for that, you're right, the workload must be split across as many cores as necessary to keep DRAM maxed out or you're throwing away performance. Luckily this problem is easily split.