LRU is a fairly intuitive and simple strategy but a rather lousy performing one. If you look at the various caches in modern CPU such as data and branch target

LRU is a fairly intuitive and simple strategy but a rather lousy performing one. If you look at the various caches in modern CPU such as data and branch target caches they have been moving away from (P)LRU as replacement strategy. The most modern one I'm aware of is DRRIP [1] in the Arm Cortex-X3 and derived V2 chips, as shown here [2] post [3]. And those are implemented in hardware, in software you are even more flexible. [1] https://en.wikipedia.org/wiki/Cache_replacement_policies#Dynamic_RRIP_(DRRIP) https://en.wikipedia.org/wiki/Cache_replacement_policies#Dyn... [2] https://i0.wp.com/chipsandcheese.com/wp-content/uploads/2023/09/neoverse_v2_ldst.png?ssl=1 https://i0.wp.com/chipsandcheese.com/wp-content/uploads/2023... [3] https://chipsandcheese.com/2023/09/11/hot-chips-2023-arms-neoverse-v2/ https://chipsandcheese.com/2023/09/11/hot-chips-2023-arms-ne...