3 ms·
But the article has tests with results, in practical terms it has actual results of it working; so is your focus on how well it actually performs? or how do we
by tankenmate 3y ago
But the article has tests with results, in practical terms it has actual results of it working; so is your focus on how well it actually performs? or how do we analyse how it achieves its results?
As to fitting most of your items in the cache; just about any cache method will work well if you can fit most things in the cache (which will typically blow out your hardware bill, ever tried to make your L3 as big as main memory?)
- xxs 3y ago>L3 as big as main memory That's not possible for many a reason, caches on the CPU die (or substrate, think AMD) tend to use the infamous 6 transistors per bit. The ones in the RAM are composed of a single transistor + capacitor, much denser. We can't have more L3 as the latency to access would pretty much make it main memory. The cache are as big as they can be, increasing their size overall doesn't contribute significant performance boost. The hardware bill is just not a thing, it's physically impossible to build very large caches that have low latency.
- tankenmate 3y agoThere are CPUs that have external (including L3) caches; and yes, off die they will have a lower latency. And that is not to mention that a cache topology uses much more power, and not just in the T6 cell itself, there's all the cache handling logic as well. But, it is possible to do; insane but possible.