Does this actually result in a routable design when used on a real FPGA? Optimizing for the lowest value of a distance metric isn't necessarily going to be ide

Does this actually result in a routable design when used on a real FPGA? Optimizing for the lowest value of a distance metric isn't necessarily going to be ideal - a highly compact placement (like the results shown) is going to require a lot of wires to pass through the center of the design. Some FPGAs may not have sufficient routing resources to support this, especially if there are many wires that cross over the center without interacting with it.