4 ms·

And here is the layout: https://www.dropbox.com/scl/fi/ksxru0lmnp0oha356fdby/layout.eps?rlkey=vxiz11vippdzck6czcbi36zoc&dl=0 https://www.dropbox.com/scl/fi/ksxr

• bcrl 3y ago
  Wow, that looks complicated. I ended up implementing the 32 bit ethernet CRC in Verilog for use on a Kintex 7 a few years ago, but I never looked at the mess of wiring that ended up generating. The code had to work with an arbitrarily wide bus as the PCIe core required a 256 bit wide bus to close timing at an achievable clock speed that was able to fully utilize PCIe x4 gen 2.