I wonder how much the massive amounts of SMT in later T-series SPARC chips (up to 8 threads/core IIRC) helped deal with this issue - if you can just spin up a n

I wonder how much the massive amounts of SMT in later T-series SPARC chips (up to 8 threads/core IIRC) helped deal with this issue - if you can just spin up a new thread with it's own set of register windows, does the OS-level context switch penalty still hurt as much?