3 ms·
Some ASIC designs are open source. That won't be down to the transistor level, but they are laid out at gate level. For example: https://tinytapeout.com/runs/
by retrac 3y ago
Some ASIC designs are open source. That won't be down to the transistor level, but they are laid out at gate level. For example: https://tinytapeout.com/runs/tt02/ https://tinytapeout.com/runs/tt02/
- jecel 3y agoWhile the tool creates the chip by placing at the gate level, the designs themselves can be studied at the transistor level if you want. You can study the actual chip gds file or look up the gds for each standard cell individually.