I've used SpinalHDL extensively for hobby projects, which is a close cousin of Chisel. The way it works there is by defining ClockDomain "areas" that contains l

I've used SpinalHDL extensively for hobby projects, which is a close cousin of Chisel. The way it works there is by defining ClockDomain "areas" that contains logic for a particular clock/reset. Signals can freely travel between different such areas, but unless you explicitly mark those signals as asynchronous, the Verilog code generator will fail with cross-domain clock violations. It's amazing. Here's an example of a clock domain crossing APB bridge: https://github.com/tomverbeure/panologic-g2/blob/ulpi/spinal/src/main/scala/cc/Apb3CC.scala https://github.com/tomverbeure/panologic-g2/blob/ulpi/spinal.... The module object takes the 2 domains as instantiation parameters: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a97035254a3800f2363c38cb3c36d2/spinal/src/main/scala/cc/Apb3CC.scala#L17 https://github.com/tomverbeure/panologic-g2/blob/9225b86011a... Here's the area with the logic that lives in the source APB clock domain: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a97035254a3800f2363c38cb3c36d2/spinal/src/main/scala/cc/Apb3CC.scala#L34-L64 https://github.com/tomverbeure/panologic-g2/blob/9225b86011a... Here is the destination APB clock domain logic: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a97035254a3800f2363c38cb3c36d2/spinal/src/main/scala/cc/Apb3CC.scala#L71-L110 https://github.com/tomverbeure/panologic-g2/blob/9225b86011a... And this is the pulse synchronizer between them: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a97035254a3800f2363c38cb3c36d2/spinal/src/main/scala/cc/Apb3CC.scala#L66-L69 https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...