I tried to use Verilog for a DIY project and found no way to control Verilog model from Python. Why is it like this? Do people really write tests directly in th

I tried to use Verilog for a DIY project and found no way to control Verilog model from Python. Why is it like this? Do people really write tests directly in this awful outdated language instead of using Python? I tried to use cocotb, but this is not what I want. It runs verilog interpreter and launches Python script from it, but I want the other way: I want to create a verilog model instance and access it in Python. Also, I found that Verilog seems to have no built-in feature for modeling real delays. Let's say we have a gate, and when input signal changes, output should instantly go to "undefined" (x) state and only after a delay switch to a valid 0 or 1 value. It seems that verilog has no such type of realistic delay built-in. I found only "transport delay" and "elastic delay", both unrealistic. I had to create my own "delay gate" to simulate this (and made lot of mistakes doing this).