> This is why I prefer VHDL. It's strongly typed. I agree, and I must say I feel much "safer" when coding in VHDL than I do in Verilog, but OTOH, VHDL's strong

> This is why I prefer VHDL. It's strongly typed. I agree, and I must say I feel much "safer" when coding in VHDL than I do in Verilog, but OTOH, VHDL's strong typing sometimes cuts the other way. I have found myself way too many times at the receiving end of VHDL's type system furiously trying to prevent me from casting something of type A to something of type B when I knew the underlying bit representation made the cast absolutely trivial.