> For example SystemVerilog has no real typing which sucks, so a typical thing to do is to build a massively improved type system for a new HDL. However in my e

> For example SystemVerilog has no real typing which sucks, so a typical thing to do is to build a massively improved type system for a new HDL. However in my experience good use of verilog style guides and decent linting tools solves most of the problem This is why I prefer VHDL. It's strongly typed. I worked at an EDA company on an HLS tool that generated HDL (Verilog, VHDL and SystemC). Customers would report linting problems with the generated Verilog. Since backend code generation was what I worked on I got to fix them. We had almost 0 problems with the generated VHDL mostly due to strong typing. But lots of issues with the generated Verilog that needed fixing. > Another typical improvement you'll find in an alternative HDL is vastly improved parameterization and generics Another area where VHDL was already there. SystemVerilog makes some improvements over Verilog.