Are you active in the SpinalHDL community? Reason for asking is this page: https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Foreword/index.html https

Are you active in the SpinalHDL community? Reason for asking is this page: https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Foreword/index.html https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/F... has an example that says for VHDL you need to write three separate processes. FWIW, that's not true, you can write it as one: process (clk, rst, cond) begin if rising_edge(clk) then if cond = '1' then my_reg <= my_reg + 1; my_reg_with_rst <= my_reg_with_rst + 1; end if; end if; if rst = '1' then my_reg_with_rst <= x"0"; end if; my_signal <= cond; end process; Also note that isn't a VHDL thing but a synthesis thing. But I think you'll be hard pushed to find a synthesiser that won't synthesise the above code correctly. Quartus, Vivado, Diamond, Libero, and ISE will all synthesise it correctly. I expect most of those tools will also accept process (all) as well, instead of having to write out the sensitivity list explicitly.