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I don’t understand how this improves upon VHDL, even after reading their own explanation[0]. Just why they think object orientation makes hardware design easier
by irdc 3y ago
I don’t understand how this improves upon VHDL, even after reading their own explanation[0]. Just why they think object orientation makes hardware design easier isn’t really explained. After a quick look at it I much prefer VHDL’s entities (though their syntax is rather too wordy for my tastes), which at least make the direction of signals clearer. The problem with libraries could have been easily solved by extending/fixing VHDL instead of going through all this effort.
0. https://stackoverflow.com/questions/53007782/what-benefits-does-chisel-offer-over-classic-hardware-description-languages https://stackoverflow.com/questions/53007782/what-benefits-d...
- ux01 3y agoDoesn't VHDL have good support for libraries? VHDL packages and subfunctions can have generics (which I've not used) for library support similar to Ada. VHDL entities can also have generics (which I have used). I was wondering what was lacking and needs extending/fixing in VHDL.
- mrmax99 3y agoHardware generator frameworks allow you to use a full-powered modern software language to control generation of hardware. Think about why it may be easier to implement something in Python than C. Adding capabilities to VHDL/SystemVerilog is very difficult since many vendors and tools have to implement it, and if any of them don't support it the whole feature can't be used.