3 ms·

I much prefer SpinalHDL, having used both.

• le-mark 3y ago
  This comment would have more value if the kind poster could provide some pros and cons.
  • cmrx64 3y ago
    After having evaluated the current state of Chisel 3, it seems most of the hard technical reasons to use Spinal have evaporated. However, when I was experimenting with both of them, Spinal's interface for simulation / testing was easier to use, and there were more metaprogramming features available. It may just be a matter of taste now!
• ux01 3y ago
  Are you active in the SpinalHDL community? Reason for asking is this page: https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Foreword/index.html https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/F... has an example that says for VHDL you need to write three separate processes. FWIW, that's not true, you can write it as one: process (clk, rst, cond) begin if rising_edge(clk) then if cond = '1' then my_reg <= my_reg + 1; my_reg_with_rst <= my_reg_with_rst + 1; end if; end if; if rst = '1' then my_reg_with_rst <= x"0"; end if; my_signal <= cond; end process; Also note that isn't a VHDL thing but a synthesis thing. But I think you'll be hard pushed to find a synthesiser that won't synthesise the above code correctly. Quartus, Vivado, Diamond, Libero, and ISE will all synthesise it correctly. I expect most of those tools will also accept process (all) as well, instead of having to write out the sensitivity list explicitly.
  • ux01 3y ago
    Ah ok, copying and pasting code into the comment box doesn't retain code formatting ...
    • ur-whale 3y ago
      Yeah, this is one of the most heinous feature of HN's comment box.
  • Dolu 3y ago
    > FWIW, that's not true, you can write it as one: While technicaly you are right, i think you missed the spirit of what the doc was saying. You may write it all in a single process, but you will always have duplicated code blocks, especialy if those 3 types of hardware (ff,ff with reset, comb) share assignements with the same condition.