3 ms·

Glad to see that RISC-V is supported as a target: https://wiki.freepascal.org/Platform_list#Supported_targets_for_RISC-V https://wiki.freepascal.org/Platform_l

• snvzz 3y ago
  RISC-V is inevitable.
• Laksen 3y ago
  The code generation has been pretty good upstream for many years now. It's easy enough The hardest part of adding full support for RISC-V is to support the hardware floating point ABI. It's incredibly complicated for likely no real world reason. It will likely require a ton of code still to make freepascal fully compliant The software and ABI ecosystem of RISC-V is what made me personally lose my love for it. The ISA is great
  • camel-cdr 3y ago
    > It's incredibly complicated for likely no real world reason Can you explain or link to somewhere to read about this? Isn't psABI quite simple?
    • Laksen 3y ago
      Sure. It's the section here https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#hardware-floating-point-calling-convention https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/ma... It's that structs of two simple fields need to be passed in registers. And more specifically that this rule is relevant for mixed integer and floating point fields. It's a very specific rule that requires a ton of code to implement compared to the integer calling convention. And again like the weird AMD64 convention likely invented to squeeze out a theoretical few cycles that never occur outside microbenchmarks