This sort of reminds me of all of the 'high-level' hardware languages that have mostly failed to catch on. As an ASIC designer, you're pretty much never limited

This sort of reminds me of all of the 'high-level' hardware languages that have mostly failed to catch on. As an ASIC designer, you're pretty much never limited by your typing speed (and much more frequently limited by tool runtimes for things like synthesis and place & route, timing analysis, etc), and across a large modern chip the difficult part is reasoning about how big distributed systems behave. A better/faster P&R tool seems ~1000x more useful than a buggy RTL generator.