3 ms·
cache latency is definitely part of what limits core clock. you're not going to have a good time if your L1 latency is, say 10 clocks. not to mention the fact
by markhahn 3y ago
cache latency is definitely part of what limits core clock. you're not going to have a good time if your L1 latency is, say 10 clocks. not to mention the fact that register files are not much different than SRAM (therefore cache-like).
- _8j50 3y agoFair enough, to measure real world performance you're right anf that's all that should matter anyways.