3 ms·
In storage, moving away from 2D MLC and TLC NAND towards 3D TLC stacking (and horrendous higher bits) has introduced disturbances that literally shorten the mem
by drtgh 3y ago
In storage, moving away from 2D MLC and TLC NAND towards 3D TLC stacking (and horrendous higher bits) has introduced disturbances that literally shorten the memory life cycle. When a cell is read, the voltage alters the state of adjacent cells, which must be forced to be rewritten to preserve their state, thus shortening the life cycle of the disk just by reading data. they are selling us crap.
From the little I understand about the problem, this would be solved by occupying more surface area to separate the tracks that run through the vertical stacks ? what would be like a 2D design surface area but with bigger complications. Although I have read papers[1] that propose adding latency in an attempt to mitigate (not solve) the problem.
So now, reading this news about processors and stacking, I wonder about what inconveniences the end users are going to suffer with processors built under these techniques. Whether in computational reliability, vulnerabilities and so on.
I wrote vulnerabilities (pure imagination and speculation of my own, I'm imagining a prefetch problem at the transistor level) because if it turns to be real at future I can see the manufacturer introducing a fix for randomly increase latencies or any other thing, and sending the computing power back ten years with an "oh, we didn't expect it such thing were possible when we designed it".
And of course the computational reliability.
is being taken care of to avoid all of this?.. if not, I leave my comment here for courts in the future.
[1] [2021] doi.org/10.1145/3445814.3446733 (use sci-hub)
[2] [2018] doi.org/10.1145/3224432 https://people.inf.ethz.ch/omutlu/pub/3D-NAND-flash-lifetime-early-retention-loss-and-process-variation_sigmetrics18_pomacs18-twocolumn.pdf https://people.inf.ethz.ch/omutlu/pub/3D-NAND-flash-lifetime...
- FirmwareBurner 3y ago>So now, reading this news about processors and stacking, I wonder about what inconveniences the end users are going to suffer with processors built under these techniques. Whether in computational reliability, vulnerabilities and so on. Denser logic hasn't got the same issues as dense non-volatile storage as logic doesn't need to have any persistence. It's what the likes of Micron and Samsung are good at fixing and working around when they launch and scale their Xnm processes for a specific storage technology, and what makes them better than competitors. Intel, TSMC, GloFo, etc they all can buy the latest gen EUV machines from ASML if they want, but yet TSMC is always one node ahead on logic and Micron and Samsung win at storage, because they're good at ironing out the kinks and challenges that come from shrinking down those specific designs closer and closer to sub-nm level while the others can not (so easily). If fabbing cutting edge silicone was as easy as just having the latest gen ASML machines, then ASML would just hoard the cutting edge machines for themselves and become vertically integrated in fabbing their own cutting chips as a side hustle before everyone else.
- dist-epoch 3y ago> they are selling us crap. You can completely rewrite a modern 4TB 3D TLC NAND every day for 3 years (3000 TBW). How is that crap? Who even has such needs? You are talking about some arbitrary "quality" - I want to be able to rewrite it a zillion times - which make no sense for 99.9% of use cases. I'd much rather have a 4 TB drive which can be rewritten 1000 times versus a same price 256 GB one which can be rewritten 1 million times.
- drtgh 3y ago>You can completely rewrite a modern [..] 3D NAND has introduced degradation when is read data from the disk. You need to calculate then how many times the disk is read, the unwritten free space that will be consumed for to maintain the data when the disk is read, and so on.
- _zoltan_ 3y agoand? the TBW guarantees are known in advance.
- drtgh 3y agoThe TBW of the disk shown in the specifications is the estimated write limit of each cell multiplied by the number of cells. They don't take into account that in order to read the data of each cell, the adjacent cells will be written and will consume little by little these estimated write limits. Therefore, if you fill the disk and only read data, it will sooner or later go into protection mode or lose data because of it. They could only guarantee the TBW if more memory were added for to cover the writes consumption by the reads usage of the current 3D NAND design. I no longer know how to explain that it is programmed obsolescence, self-destructing disks by read data. We stopped seeing 10 years guaranties when 3D NAND was introduced, so they know well what they are doing.
- fomine3 3y agoI don't think so https://www.jedec.org/standards-documents/focus/flash/solid-state-drives https://www.jedec.org/standards-documents/focus/flash/solid-...