5 ms·
Anyone have insight on: Why don’t they position the SOC to have the HBM in the center with the CCDs and XCDs on the perimeter? Seems to me that would yield lo
by yazaddaruvala 3y ago
Anyone have insight on:
Why don’t they position the SOC to have the HBM in the center with the CCDs and XCDs on the perimeter?
Seems to me that would yield lower “wire length” through the interconnect for each CCD/XCD to all of the memory.
- wtallis 3y agoEach memory chip is connected to a single DRAM controller. Those DRAM controllers are what you'd want to be close to each other to minimize NUMA effects.
- soganess 3y agocomplete and total unfounded guess... thermal expansion?
- PedroBatista 3y agoMaybe thermals? Idk
- jauntywundrkind 3y agoThe memory isn't designed to connect to a lot of different chips. So there's no reason to put it in the center. The core systems of interconnect are at the base most center-most (well, there's a passive interposer too, but it's just wires): the IOD. These intermediate connections across the chips on top of them, the IOD next to them, and the memory.
- brucethemoose2 3y agoThe XCDs need to talk to each other very quickly, way faster than the HBM, to act like a single chip. Also, the physical interconnect between the XCDs is different than the HBM.
- deleted 3y ago[deleted]
- thrtythreeforty 3y agoHBM is designed for the wire lengths that you're talking about. The core protocol isn't so terribly different from good old DDR4. The die-to-die links, on the other hand, have extremely short wire length limits (less than a centimeter iirc for UCIe). At the physical layer, you just waste a bunch of power and area driving a high voltage to make the signal go further. Do that enough and you basically wind up with a PCIe PHY.