I’m working on a simulator for a subset of VHDL in Racket Scheme, because I’ve recently become interested again in digital logic and FPGAs. I’m starting with m

I’m working on a simulator for a subset of VHDL in Racket Scheme, because I’ve recently become interested again in digital logic and FPGAs. I’m starting with manually translating VHDL into Racket to get a feel for it and how to model it. The goal is to implement a language extension for VHDL with the help of the Beautiful Racket book.