I've worked on high availability systems where CPUs were duplicated for reliability. In one product - which I won't name here - the surrounding ASICs were cons

I've worked on high availability systems where CPUs were duplicated for reliability. In one product - which I won't name here - the surrounding ASICs were constructed of "self-checking logic" - where every data path had parity and all logic elements were designed such that no single wire failure could go undetected. The idea was that with near 100% reliability, a compute module could flag itself defective before recent work by it could be "committed" into the main memory which was transaction based (every segment of which also had to have at least two redundant copies in different modules). But who will sell you a self-checking CPU? So use two of them and compare everything they do from reset. This may not be so easy with modern CPUs with huge internal clock rates - who says that they will emerge from asynchronous reset in step, for example? But with 1990s technology it was fine.