3 ms·
The previous DVINO was a 5-stage in-order, this Sargantana core is a 7-stage out-of-order write-back with register renaming and a non-blocking memory pipeline.
by ansible 3y ago
The previous DVINO was a 5-stage in-order, this Sargantana core is a 7-stage out-of-order write-back with register renaming and a non-blocking memory pipeline.
So it is not a full in-order or a full out-of-order design.
- galangalalgol 3y agoAre the vector extensions the fixed size ones or the originally proposed lanecount agnostic ones? That is the aspect of riscv i'm most excited about.