3 ms·

Does anyone know what this "bug" manifests as? Your first sentence implies it's a lockout created at reset, but your second implies it manifests post-reset thro

Does anyone know what this "bug" manifests as? Your first sentence implies it's a lockout created at reset, but your second implies it manifests post-reset through user/programmer action.

toast0 3y ago
I think they're saying you get to run one CCX at a time; either the A57 cores or the A53 cores and you can only change that once after a reset. Presumably the boot time CCX is selected by selection pins. Depending on exactly what reset means, this might be something like the i286 that couldn't leave protected mode without a reset, so systems were built for OSes that entered protected mode where they could set up a reset vector and then cause a reset and jump back to their real mode kernel. Or, it might be a very intrusive reset that results in memory contents being reset --- that's not going to be something worth engineering around. Either way, it's easier to just only use the A57 cores to begin with, and especially if switching between the two is problematic.
- colejohnson66 3y ago
  Assuming it is some "at reset" selection, Nvidia advertising it as an eight-core chip would be deceptive, so I'm reluctant to believe such a theory. I wouldn't put it past marketing to do such a thing, but later revisions of the manual don't mention the A53 cores, so I'm inclined to believe it's a hardware bug. Unfortunately, without someone from inside Nvidia telling us, all we have are rumors and no evidence.
  - toast0 3y ago
    ARM big.LITTLE systems started out as use one or the other, but not both simultaneously. Advertising those as 8 core when it's really big 4 or LITTLE 4, or later incantations where you could use the big or LITTLE of each of the four paired processors, is sketchy, but was common. If the plan was to allow big 4 or LITTLE 4, and then a hardware bug became apparent that you could switch to LITTLE cores but not back to big cores, well you notify customers and stop advertising the LITTLE cores. archive.org has them mentioned Jun 1 2016 [1], and then removed Jun 14, 2016 [2]; the A53 cores aren't mentioned but are shown in the die map on the current page [3]. [1] https://web.archive.org/web/20160601063237/http://www.nvidia.com:80/object/tegra-x1-processor.html https://web.archive.org/web/20160601063237/http://www.nvidia... [2] https://web.archive.org/web/20160614200203/http://www.nvidia.com:80/object/tegra-x1-processor.html https://web.archive.org/web/20160614200203/http://www.nvidia... [3] https://developer.nvidia.com/content/tegra-x1 https://developer.nvidia.com/content/tegra-x1
- monocasa 3y ago
  Yeah, I'm saying that I've heard that there's some bug that's only hit by running one CCX after you've run the other one. > Presumably the boot time CCX is selected by selection pins. There's actually another core, an ARM 7 referred to as the BPMP (Bootstrap and Power Management Processor IIRC), that handles main CCX bring up.

Does anyone know what this "bug" manifests as? Your first sentence implies it's a lockout created at reset, but your second implies it manifests post-reset through user/programmer action.

toast0 3y ago

I think they're saying you get to run one CCX at a time; either the A57 cores or the A53 cores and you can only change that once after a reset. Presumably the boot time CCX is selected by selection pins. Depending on exactly what reset means, this might be something like the i286 that couldn't leave protected mode without a reset, so systems were built for OSes that entered protected mode where they could set up a reset vector and then cause a reset and jump back to their real mode kernel. Or, it might be a very intrusive reset that results in memory contents being reset --- that's not going to be something worth engineering around. Either way, it's easier to just only use the A57 cores to begin with, and especially if switching between the two is problematic.

colejohnson66 3y ago
Assuming it is some "at reset" selection, Nvidia advertising it as an eight-core chip would be deceptive, so I'm reluctant to believe such a theory. I wouldn't put it past marketing to do such a thing, but later revisions of the manual don't mention the A53 cores, so I'm inclined to believe it's a hardware bug. Unfortunately, without someone from inside Nvidia telling us, all we have are rumors and no evidence.
- toast0 3y ago
  ARM big.LITTLE systems started out as use one or the other, but not both simultaneously. Advertising those as 8 core when it's really big 4 or LITTLE 4, or later incantations where you could use the big or LITTLE of each of the four paired processors, is sketchy, but was common. If the plan was to allow big 4 or LITTLE 4, and then a hardware bug became apparent that you could switch to LITTLE cores but not back to big cores, well you notify customers and stop advertising the LITTLE cores. archive.org has them mentioned Jun 1 2016 [1], and then removed Jun 14, 2016 [2]; the A53 cores aren't mentioned but are shown in the die map on the current page [3]. [1] https://web.archive.org/web/20160601063237/http://www.nvidia.com:80/object/tegra-x1-processor.html https://web.archive.org/web/20160601063237/http://www.nvidia... [2] https://web.archive.org/web/20160614200203/http://www.nvidia.com:80/object/tegra-x1-processor.html https://web.archive.org/web/20160614200203/http://www.nvidia... [3] https://developer.nvidia.com/content/tegra-x1 https://developer.nvidia.com/content/tegra-x1
monocasa 3y ago
Yeah, I'm saying that I've heard that there's some bug that's only hit by running one CCX after you've run the other one. > Presumably the boot time CCX is selected by selection pins. There's actually another core, an ARM 7 referred to as the BPMP (Bootstrap and Power Management Processor IIRC), that handles main CCX bring up.