Register-register or immediate ops are 2 cycles (e.g. TXA, LDA #imm). Register-ZP ops are 3 cycles. Register-absolute (full 16-bit address) are 4 cycles. Ind

Register-register or immediate ops are 2 cycles (e.g. TXA, LDA #imm). Register-ZP ops are 3 cycles. Register-absolute (full 16-bit address) are 4 cycles. Indirect lookups add a cycle, indexed adds a cycle. There is some weirdness - e.g. pushing A to the stack is 3 cycles, but pulling it back is 4 cycles. And LSR/ASL start at 5 cycles for ZP access (6 for absolute) and you would think bit shifting would be super fast.